DC to DC voltage converter

ABSTRACT

The DC to DC voltage converter consists of two single ended pulse width modulated converters with a single voltage control loop, a power balancing control loop and overload protection circuitry. The converters which share the same input and output filters are staggered in time so as to reduce the pulse current in the input filter capacitor and the ripple current in the output filter capacitor thereby permitting a reduction in the size of the input and output filters.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to DC voltage converters which convert a directcurrent power input at one voltage level to a direct current poweroutput at a different voltage level, and more particularly to theapplication of staggered mode switching to single-ended,pulse-width-modulated, DC to DC converters, thereby, combining thebenefits of a transformer coupled supply with the benefits of staggeredmode switching.

2. Description of Prior Art

The use of staggered mode switching to reduce the RMS value of the ACcurrents and voltages inherent in switching regulators and the resultingimprovement in output ripple voltage and filter size and cost have beendisclosed in the art.

Staggered mode switching has been applied in the prior art with one ormore of the following disadvantages:

1. No DC isolation between the input and output.

2. A restriction in the nominal voltage transformation ratio in order toreceive the maximum benefit obtainable from staggered mode operation.

3. Current steps in the output filter capacitor require the capacitor tohave a very low impedance over a wide frequency range to control theripple and switching spikes in the output voltage.

4. A circuit topology that does not reduce the RMS AC currents andvoltages to the degree that it is achievable through the staggered modeoperation of two single ended converters.

5. More than two power transistors are required.

6. More than one voltage control is required.

7. More than one overload protection circuit is required.

8. Accurate balance of the power and stress levels between theconverters or power channels cannot be achieved.

9. Power transformer windings are operated at a lower duty cycle thusadding to their size and weight.

10. High pulse current in the output capacitor over most of the inputvoltage range greatly increases the size, weight and cost of the outputfilter capacitor.

11. The converter must be protected against simultaneous conduction ofthe power switching transistors.

12. A blocking capacitor or some other means to control the dc fluximbalance in the power transformer is required since the transformercannot be allowed to saturate at either end of the cycle.

Accordingly, it is an object of the present invention to provide a DC toDC converter that has a combination of characteristics which will enableit to overcome the aforementioned disadvantages and which make itparticularly well suited to the requirements of avionic equipment. Suchavionic equipment requirements which this novel invention can meetinclude small size and weight, the utilization of low profile componentsso as to be compatible with standard hardware module packaging, atwo:one input voltage range, high efficiency, operability over a widecomponent temperature range (minus 55° C. to ±125° C.) and highreliability.

SUMMARY OF THE INVENTION

The foregoing objects are achieved according to this invention throughthe utilization of a closed loop system which controls the switching oftwo single ended, pulse width modulated DC to DC converters in such amanner as to minimize the input ripple current and output ripplevoltage.

The DC input voltage is first fed through an input filter connected byway of a switching means to each of two single ended DC to DC converterswhich are in turn connected to an output filter. As the input voltagechanges from its nominal value, the control means adjusts the switchingmeans in such a manner as to keep the output voltage at a constant DClevel while minimizing any AC components.

A power balancing means is employed to ensure that the load is sharedequally by the two single ended converters. This is achieved by allowingthe controller to make a slight change in the duty cycle of one singleended converter with respect to the other. An overload protection meansis included to limit the current flowing in the circuit elements and thedistribution system to a safe level during an overload or short circuitcondition.

BRIEF DESCRIPTION OF THE DRAWINGS

Various other objects, features and attendant advantages of the presentinvention will be more fully appreciated from the following detaileddescription in connection with the accompanied drawings.

FIG. 1 is a schematic diagram of an embodiment of a staggered mode DC toDC converter according to the invention.

FIG. 2 illustrates some of the voltage waveforms present in thecontroller portion of the DC to DC converter.

FIG. 3 illustrates some of the current and voltage waveforms present inthe staggered mode DC to DC converter when E_(IN) and E_(OUT) are set attheir nominal values.

FIG. 4 illustrates some of the current and voltage waveforms present inthe staggered mode DC to DC converter when E_(IN) is increased toapproximately 160 percent of its nominal value.

FIG. 5 illustrates some of the current and voltage waveforms present inthe staggered mode DC to DC converter when E_(IN) is decreased toapproximately 70 percent of its nominal value.

FIG. 6 is a schematic diagram of a reset circuit which could be usedwith the instant invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A schematic diagram of the staggered mode DC to DC voltage converter isshown in FIG. 1. Such an embodiment for a single output power supply inthe 200 to 1000 watt range, such as a 60 ampere, 5 volt logic supplyoffers advantages that are significant in many military and commercialapplications. The invention will be described with reference to its usein a military environment which poses strict requirements upon itsoperation e.g., operability within a temperature range from -55° C. to125° C.

In the avionic environment, the available 3 phase, 400 Hertz, 115/200VAC can be passed through a bridge rectifier in order to obtain a DCnominal input voltage, E_(IN) of 270 volts when the input AC voltage isat its nominal value of 113 VAC.

Referring more particularly to FIG. 1, the input DC voltage E_(IN) isconnected across the input filter consisting of a first inductor 2 and afirst capacitor 4. After the input DC voltage has been filtered in thismanner, it serves as the source voltage for each of the two single endedconverters. Notice that two ground designations are shown in FIG. 1 inorder to demonstrate DC isolation can be achieved between the input andoutput voltages. It should be noted that the invention is also operablewith the designated grounds in common with one another.

The first single ended DC to DC converter is composed of a single endedpower transformer 6, diodes 8 and 10, inductor 12, transistor 14 andresistor 30. Transistor 14 functions as a switching means to applyE_(IN) across the primary windings of transformer 6. Less than 1% ofE_(OUT) is dropped across resistor 30. The transformer polarity dotsshown in FIG. 1 correspond to the start of each winding. Inductor 12serves as a current averaging means.

The second single ended DC to DC converter consists of a single endedpower transformer 16, diodes 18 and 20, inductor 22, transistor 24 andresistor 32. Transistor 24 functions in a complementary fashion withrespect to transistor 14, as it acts as a switching means to sendcurrent through the primary windings of transformer 16. Inductor 22serves as a current averaging means.

Controller 26 acts as a control means which operates transistors 14 and24 in an out of phase fashion thereby alternately driving transistors 14and 24 in conducting and nonconducting states, respectively. Undernormal operating conditions controller 26 will be turning eachtransistor 14 and 24 on and off 50% of the time. This will cause each ofthe two single ended converters to have a 50% duty cycle. Under theseconditions since the corresponding components of each single endedconverter are identical, when the input voltage E_(IN) and outputvoltage, E_(OUT), are set at their nominal values, the ripple currentpassing through inductor 12, I₁₂, will be equal and of opposite polarityto the ripple current passing through inductor 22, I₂₂. The currentI_(L) being the sum of currents I₁₂ and I₂₂, is in the ideal case a pureDC current because the equal and opposite ripple currents haveeffectively cancelled each other out.

The output filter capacitor 28 is common to both single endedconverters. If the AC component of I₁₂ and I₂₂ do not completely cancel,there will be an AC component to I_(L) which is shunted to ground bycapacitor 28.

The voltage across capacitor 28, the output voltage E_(OUT) is fed backto controller 26, closing the voltage control, servo loop.

The control means, controller 26, contain error amplifier 76 whichcompares the output voltage, E_(OUT), with a positive reference voltage,V_(REF). Impedance networks 96 and 98 control the frequency-gainresponse of the error amplifier and are used to optimize thecharacteristics of the output voltage control servo. V₅ is the amplifiedvoltage difference between E_(OUT) and V_(REF). Controller 26 alsocontains a two phase oscillator 50 which generates two triangularwaveforms (φ1 and φ2) that are 180° out of phase from one another (seeFIGS. 2a and 2c). FIG. 2a represents waveforms of the voltages at theinput terminals of voltage comparator 52 and FIG. 2b represents theoutput voltage, V₈, of voltage comparator 52. Notice that when the V₅waveform exceeds the φ1 waveform, the output waveform V₈ experiences apositive state. This time duration of this positive state is denoted byT_(ON) and the total period of the triangular waveform is denoted byT_(P). Voltage comparator 54 has the input voltages of V₇ and φ2, and anoutput voltage of V₉. If the voltage at V₆ of FIG. 1 is equal to thevoltage at V₅, then V₅ will equal V₇ and the waveforms at V₈ and V₉ willbe identical to each other except for a displacement in time equal to180° or one-half the period. If, however, the voltage at V₆ is morepositive than that at V₅ then V₇ will be more positive than V₅ as shownby the dashed line in FIG. 2c. This will result in a new waveform havinga higher duty cycle (ratio of T_(ON) to T_(P)) for V₉ as shown in thedashed waveform of FIG. 2d. Transistors 14 and 24 are turned "on" duringthe high states of V₈ and V₉ respectively. Accordingly, the averagevalue of V₁₃ will be higher than the average value of V₁₂ if the dutycycle of V₉ is greater than the duty cycle of V₈. This will cause I₂₂ toexceed I₁₂ and I₆ to exceed I₅, resulting in a negative sample voltageat "b" greater (in magnitude) than that at "a". If the voltage at "b"exceeds that at "a", V₆ will be driven in the negative direction,reducing the duty cycle of V₉ with respect to V₈. Equilibrium of thebalance control loop will be achieved when I₅ equals I₆. Notice that thepulse train at V₈ remains perfectly interlaced with the pulse train atV₉, regardless of the voltage at V₆. This is necessary to minimize theAC currents flowing through capacitors 4 and 28 thereby minimizing theoutput ripple voltage, the dissipation (due to equivalent seriesresistance) in capacitors 4 and 28, and the conducted noise current onthe input power line. Current balance (I₅ equals I₆ and I₁₂ equals I₂₂)is necessary to balance the stress levels in the circuit components andalso minimize the RMS current that must be filtered by the input filter.

Drivers 80 and 82 function to provide the proper magnitude of basecurrents to transistors 14 and 24, respectively, when the waveforms atV₈ and V₉, respectively, are at their high states. Transformer couplingprovided by transformers 84 and 86 is utilized between each driver andeach transistor in order to match impedances for the most efficient basedrive possible. Another advantage of transformer coupling between eachdriver and transistor is that it provides dc isolation at this point inthe circuit.

Resistors 92 and 94 serve as an attenuator of variations in V₆. It isnecessary to make V₇ slightly different than V₅ in order to accommodateimbalances that appear elsewhere in the circuit e.g., differences instorage times between transistors 14 and 24. In order to vary V₇ withrespect to V₅, we need to couple a small amount of the voltage developedat the output of the balance circuit, V₆ and have it appear at V₇. Thevoltage divider comprising resistors 92 and 94 couples a portion of thatbalance correcting voltage, V₆, onto V₇. The voltage, V₇, is differentfrom the voltage V₅ in such a manner as to take up all the otherimbalance problems that exist in the circuit.

FIG. 3 illustrates some of the current and voltage waveforms present inthe staggered mode DC to DC converter when E_(IN) and E_(OUT) are set attheir nominal values. The voltage waveforms for V₁₂ and V₁₃ are shown inFIGS. 3a and 3c respectively. Notice that V₁₃ is identical to V₁₂ exceptthat it is shifted 180° because switching transistors 14 and 24 are outof phase with respect to one another.

The current waveforms I₁₂ and I₂₂ shown in FIGS. 3b and 3d represent thecurrent through inductors 12 and 22, respectively. Since the ACcomponents of I₁₂ and I₂₂ are equal and of opposite polarity from oneanother, the resultant output current, I_(L), is pure DC as shown inFIG. 3e and the current through capacitor 28, I₂₈ is zero.

The current waveforms I₁₄ and I₂₄ are shown in FIG. 3f and 3g, and theircombination I, is shown in FIG. 3h. The AC component of I, is thecurrent through capacitor 4, I₄. Notice that I₄ as shown in FIG. 3j ismuch less than the AC components of either I₁₄ or I₂₄. This lower ACcurrent significantly reduces the task of the input filter which meansthat the size of capacitor 4 and inductor 2 can be greatly reduced. Eventhough the RMS value of I₄ increases significantly during voltagesurges, the thermal time constant of capacitor 4 is much larger than theduration of a line surge. For example, in aircraft electrical systems,the quality of the power is specified by MIL-STD-704B which sets theoperational voltage limits between 80 and 180 VAC. The maximum durationthat the voltage can be at either extreme is 10 milliseconds. Capacitor4 has a thermal time constant such that it can tolerate or absorb a muchhigher RMS ripple current for a short period of time, e.g., 10milliseconds.

The instant invention provides for the utilization of smaller componentsin the input and output filters even when variations occur in the inputvoltage level E_(IN). For example, when the input voltage E_(IN) isincreased to approximately 160% of its nominal value, the significantcurrent and voltage waveforms associated with the instant inventionwould appear as they do in FIG. 4. Notice that the AC component of I_(L)in FIG. 4e, I₂₈, has twice the frequency and approximately half theamplitude of either I₁₂ or I₂₂ as shown in FIGS. 4b and 4d. Furthermore,the present invention still provides significant improvement in theratio of the average of the input current I_(IN) to the current throughcapacitor 4, I₄. Therefore, the size, weight and cost of the input andoutput filters can still be significantly reduced.

A power balancing means is necessary in order to insure that themagnitude of I₁₄ equals that of I₂₄ and hence the magnitude of I₁₂equals that of I₂₂. This is necessary in order to minimize the ACcurrent component of I_(L) and to balance the current and thermal stresslevels in the corresponding components of the two single endedconverters. The voltage developed across sense resistors 30 and 32 willbe equal if I₅ (which is identical to I₁₂) is equal to I₆ (which isidentical to I₂₂). If an imbalance of these currents exists thecorresponding imbalance voltage will be amplified by operationalamplifier 28 producing a correction voltage V₆ which slightly changesthe duty cycle of transistor 24 with respect to transistor 14 so as toachieve balance.

Resistance 30 and 32 have equal resistance values. Resistor 34 is merelya gain setting resistor which sets the response of this integratorcircuit. Capacitor 36 is the feedback capacitor for operationalamplifier 28. Resistor 88 and capacitor 90 are used to smooth thevoltage waveform at V₁₅.

The voltages across resistors 30 and 32 are also used by an overloadmeans as they are summed by resistors 38 and 40 in order to provideoverload protection. Voltage comparator 42 is utilized in order tocompare voltage V₂ with a reference voltage V₁. The voltage V₂ isproportional to the voltages at "a" and "b" developed across resistors30 and 32 respectively. If V₂ exceeds V₁, output voltage of comparator42 will go to the high state.

Resistors 60 and 61 of the overload means function as a voltage dividerin order to independently set the V₁ violtage with respect to -V_(REF).Capacitor 62 is used to smooth the voltage waveform V₂. Diode 64 is usedto couple the positive or the high state of the output from voltagecomparator 42 into the R-C network comprising resistor 66 and capacitor68.

Voltage comparator 70 compares the voltage developed across capacitor 68to a reference voltage and should V₃ exceed V_(REF), the output ofvoltage comparator 70 will go to a high voltage state. Diode 72 couplesthis high voltage to capacitor 74 thereby charging capacitor 74.

When V₄ is at this high state, resistor 78 couples this high voltage toerror amplifier 76 of controller 26. The ratio of the resistivecomponent of impedance network 98, to the value of the resistance ofresistor 78 is sufficiently high so that the high state voltage at V₄will cause the output of operational amplifier 76 to go to its mostnegative state resulting in a zero duty cycle at V₈ and V₉. During thiszero duty cycle interval transistors 14 and 24 will be continuously offand the voltages at "a" and "b" developed across resistors 30 and 32will be zero. Correspondingly, the voltage at V₂ will go to zero and,therefore, will be above the voltage V₁. This will cause the output ofvoltage comparator 42 to be driven to its low voltage state, allowingcapacitor 68 to discharge. When the voltage V₃ decreases to a valuebelow V_(REF), the output of voltage comparator 70 is driven to its lowvoltage state, which allows the voltage V₄, across capacitor 74 todecay. Once V₄ decays to a sufficiently low value, the output ofoperational amplifier 76 will begin to rise. The duty cycle at V₈ and V₉will accordingly increase slowly from zero to some larger value. As thishappens the collector currents in transistors 14 and 24 will increase.Should the overload condition still exist, they will increase to a pointwhere the voltage V₂ will again exceed the voltage V₁ and the overloadmeans will be driven back into the overload state characterized by azero duty at V₈ and V₉ and transistors 14 and 24 have zero currents onceagain. This process will repeat itself on a repetitive basis untileither the overload condition is removed or the supply is manuallyturned off.

As previously stated both voltage comparators 42 and 70 are eachfollowed by an RC network. The first RC network comprised of resistor 66and capacitor 68 determines the dead time between attempted restarts.The second RC network comprised of resistor 78 and capacitor 74determines the rate at which the supply comes up during its activeportion of the overload cycle. By setting the time constant of the firstRC network much longer than the time constant of the second RC network,the dead time between restart attempts will be much longer than theactive portion of the restart cycle. The average value of the outputcurrent, I_(O) can be made low simply by increasing the amount of deadtime with respect to the active time. Although the peak currents of theoutput current will still be whatever it takes to trip the threshold atV₂, the average output current under short circuit conditions issubstantially reduced thereby minimizing the possibility of burning outinterconnection wiring without latching the power supply off or usingcurrent foldback techniques which can hang up under certain loadconditions.

In an effort to present typical component values for the instantinvention and elucidate upon the design philosophy, the steps necessaryto design a power supply to meet the requirements of a specificationsuch as Military Specification MIL-STD 704B will be described. It willbe assumed that the power supply will be operating at 20K Hertz and havean output voltage, E_(OUT), equal to 5 volts DC and an output current I₀equal to 60 amps. Furthermore, the supply shall have a maximum outputripple voltage of 0.1 volt peak to peak, a nominal efficiency of 80% andan operating temperature range of -55° C. to +55° C. With the threephase voltage at its nominal value of 113 VAC, the input voltage,E_(IN), would be equal to 270 volts DC. Since the staggered mode DC toDC converter is to operate at a 50% duty cycle (the optimum operatingpoint for this invention), the turns ratio for transformers 6 and 16must be equal to E_(IN) /(E.sub. OUT /0.5+0.75) or 23:1. The 0.75 voltsused in the aforementioned equation represents the rectifier and copperlosses. The variation in the current I₁₂ as shown in FIG. 3b is chosento be approximately 50% of the average value of I₁₂ or 14 amps. Thevalue of inductor 12 necessary to achieve this is equal to (5 volts) (25microseconds)/14 amps or 9 microhenries. The 25 microseconds represent ahalf period because the supply is operating at 20K Hertz and at a 50%duty cycle. Inductor 22 will have the same value as inductor 12. For thefirst 25 microseconds (0<t<25 microseconds), V₁₂ is positive andtransistor 14 and diode 8 are conducting. Diode 10 is reverse biased,hence nonconducting. Therefore, the current through diode 8 and, hencethe secondary of transformer 6 is equal to I₁₂. The primary current, I₁₄of transformer 6 is therefore I12/23, where 23 is the primary tosecondary turns ratio. During the second 25 microseconds (25<t<50microseconds), diode 8 is reversed biased and I₁₂ flows through diode10. Not shown is a reset circuit that resets transformer 6 to minusB_(max) during the off period of transistor 14. The operation oftransformer 16 and its associated components are the same as transformer6 except of a displacement in time of a half period.

The RMS value of I₄ shown in FIG. 3j is approximately 0.2 amperes. Thismeans that capacitor 4 can be realized by combining only twoM39018/1A-0774 capacitors (series connected to achieve necessary voltagerating) to handle the 0.2 amp RMS ripple current.

When the avionic input line voltage is at its high level of 180 volts AC(line to neutral), E_(IN) will be 430 volts DC and the duty cycle of thesupply will be 28% calculated from the following relationship: ##EQU1##

For this condition, the current through capacitor 28, I₂₈, will beapproximately 10 amperes, peak to peak (FIG. 4e). Solid tantalumcapacitor (such as M39003/03) are generally selected for the outputcapacitor because they maintain a low equivalent series resistance, ESR,(0.1 ohms for a 15 volt, 330 microfarad unit) at -55° C. In order tocomply with a 0.1 volt peak to peak ripple voltage, the ESR of capacitor28 cannot exceed 0.01 ohm. Hence ten M39003/03-0145 capacitors inparallel are required to perform the function of capacitor 28.

When the avionic input line is at its low level of 80 volts ac, the dutycycle of the converter will be 68% and as can be seen in FIG. 5 thecurrent through capacitor 28, I₂₈, will be approximately 4 amperes peakto peak, corresponding to an output ripple of 0.04 volts peak to peak.

Avionic power supplies according to the aforementioned design have beenbuilt to achieve better than 5.5 watts per cubic inch, 100 watts perpound and 80% efficiency at full load over an input voltage range of 90VAC to 180 VAC.

One disadvantage of a single ended converter as compared to a fullbridge circuit is that the switching transistors must have a higherV_(CEX) rating. When E_(IN) =430 the duty cycle is 28% and the resetvoltage referred to the primary of the power transformer must be atleast 430 (28/72)=111 volts. Thus the V_(CE) at high line will be atleast 541 volts. In a practical case the actual V_(CE) will have amaximum value of 650 to 750 volts depending on the speed of the servoloop. However, only the first 430 volts of the V_(CE) voltage swing areunder load since the catch diode will provide the output current whenthe polarity of the transformer reverses. Hence, both the bridgeconverter and the single ended converter have the same V_(CEX) (SUS).However, the V_(CEX) rating for the bridge converter and thesingle-ended converter are 430 and 750 volts, respectively. A transistorthat has a V_(CEX) (SUS) of 430 volts will typically have a V_(CEX) inthe range of 600 to 800 volts and the higher V_(CEX) requirement of thesingle ended converter is of little consequence.

In determining the maximum V_(CEX) (SUS) for the transistor in thebridge converter it was assumed that one of the two conductingtransistors could turn off before the other causing the full inputvoltage to be dropped across a single transistor.

In each single ended converter, the transformer is reset by a resetwinding (not shown in FIG. 1) in order to reset the flux density of eachtransformer to -B_(Sat) during the time that each switching transistoris turned off. This results in swinging the flux density from -B_(Sat)to +B_(max). -B_(SAT) is the saturation flux density in the negative(Third Quadrant) direction and B_(max) is the highest positive value theflux density experienced during normal operation. No capacitor isnecessary to balance the flux swing as is required in a power supplyutilizing a bridge circuit. In a prior art bridge circuit supply anunbalance current can build up due to an average voltage across theprimary of the power transformer. This can significantly reduce theavailable flux swing. In such systems a capacitor is inserted in serieswith the primary in order to insure that no average current can flowthrough the primary which would cause a DC flux bias. Since thecapacitor must be bipolar and capable of handling the same RMS currentthat flows through the input capacitor it must be large in size andcostly.

Bridge circuits operating at nominal input voltages have their onetransformer operating with a conduction angle of approximately 63% forits primary and 31.5% for the secondaries.

The conduction angles of the primary and secondary (at nominal inputvoltage) are both 50% for the instant staggered mode power supply. Thisoffers a slight average from a copper utilization standpoint. Therefore,by swinging to a slightly higher flux density and having a slightlyhigher utilization of the copper, the combined size and weight of thetwo 150 watt transformers 6 and 16 will be somewhat smaller than the one300 watt transformer required in a comparable bridge circuit powersupply.

Furthermore, using prior art design techniques, such as that describedin TRW Power Semiconductors Application Note No. 122A (2/76), a fivevolt prior art power supply would require much larger capacitors in theinput and output filters, for a given load current.

While a preferred embodiment of the invention has been shown anddescribed, various other embodiments and modifications thereof willbecome apparent to persons skilled in the art, and will fall within thescope of invention as defined in the following claims. In higher outputcurrent version it may be desirable to use pulse transformers to samplethe primary currents of transformers 6 and 16 instead of using resistorsthat must conduct the output current in order to perform the currentbalance and overload protection functions.

One technique for resetting the power transformer is to add a resetwinding to each transformer, and connect the reset windings in a seriesaiding configuration as shown in FIG. 6. A small choke and a resistorare used to maintain a constant current through the reset windings.Since the transformers are operating out of phase, V_(R) is smallcompared to the output voltage of each reset winding thus making thetask of L_(R) much easier. R_(R) sets the value of the reset current,I_(R), and L_(R) minimizes variations in I_(R) due to overlap (dutycycle greater than 50%), underlap (duty cycle less than 50%) andsaturation (at B_(SAT)) of the power transformers at the end of resetperiod. The reset power is approximately one watt for a 300 watt supply.

What is claimed as new and desired to be secured by Letters Patent ofthe United States is:
 1. A staggered mode DC to DC voltage converter forconverting an input DC signal subject to voltage variations to aregulated output DC voltage comprising:an input filter consisting of afirst inductor and first capacitor connected in series, having saidinput DC signal applied across said inductor and capacitor; a firstsingle ended converter having a first and second input terminal, saidfirst input terminal being connected to said input filter at a pointlocated between said first inductor and said first capacitor, and saidsecond input terminal being connected to a first switching means so asto switch said first single ended converter to a conducting ornonconducting state at specific times, said first single ended converterfurther comprising a first transformer means whose output current isfirst rectified by a first rectification means being connected to bothends of said first transformer means and then averaged by a firstaveraging means to yield a first average current; a second single endedconverter having a first and second input terminal, said first inputterminal being connected to said input filter at a point located betweensaid first inductor and said first capacitor, and said second inputterminal being connected to a second switching means so as to switchsaid second single ended converter to a conducting and nonconductingstate at specific times, said second single ended converter furthercomprising a second transformer means whose output current is firstrectified by a second rectification means being connected to both endsof said second transformer means and then averaged by a second averagingmeans to yield a second averaged current; a control means having a firstand second output terminal connected to said first and second switchingmeans to switch said second single ended converter to a conducting ornonconducting state at specific times when said first single endedconverter is switched to a nonconducting or conducting staterespectively; an output filter having a first and second terminal, saidfirst terminal being connected to said first and said second singleended converters to accept the d.c. and a.c. components of said firstand second averaged current, said a.c. currents being out of phase withone another combining so as to reduce the ripple current in said output,said first terminal of said output filter being connected to a firstinput terminal of said control means; and a power balancing means forequally balancing the power between said first and second single endedconverters and providing a balance signal to said control means toadjust the specific times that said first and second switching means areturned on and off.
 2. The staggered mode DC to DC converter set forth inclaim 1 further comprising an overload means having one end connected tosaid first single ended converter to sense a first voltage proportionalto a first averaged current and having a second end connected to saidsecond single ended converter to sense a second voltage proportional toa second averaged current so that said control means can turn off saidDC to DC converter in the event an overload conditions arises.
 3. Thevoltage converter set forth in claim 1 wherein said first single endedconverter comprises:a first single ended power transformer, having thestart end of its primary winding connected to said first input terminalof said first single ended converter and having the other end of itsprimary winding connected to said second input terminal of said firstsingle ended converter; a first diode element whose anode end isconnected to the start end of the secondary winding of said first singleended power transformer; a second diode element whose cathode end isconnected to the cathode end of said first diode element and whose anodeend is connected to the other end of the secondary winding of said firstsingle ended power transformer; a second inductor whose first end isconnected to the cathode end of said second diode element and whosesecond end is connected to said first input terminal of said outputfilter; and a first resistor, having one end connected to the anode endof the second diode and having the other end connected to the saidsecond input terminal of said output filter.
 4. The voltage converterset forth in claim 3 wherein said second single ended convertercomprises:a second single ended power transformer, having the start endof its primary winding connected to said first input terminal of saidsecond single ended converter and having the other end of its primarywinding connected to said second input terminal of said second singleended converter; a third diode element whose anode end is connected tothe start end of the secondary winding of said second single ended powertransformer; a fourth diode element whose cathode end is connected tothe cathode end of said third diode element and whose anode end isconnected to the other end of the secondary winding of said secondsingle ended power transformer; a third inductor whose first end isconnected to the cathode end of said fourth diode element and whosesecond end is connected to said first input terminal of said outputfilter; and a second resistor, having one end connected to the anode endof the fourth diode and having the other end connected to the saidsecond input terminal of said output filter.
 5. The voltage converterset forth in claim 3 wherein said first switching means comprises afirst transistor having a collector, base and emitter terminal saidcollector terminal being connected to said other end of said primarywinding of said first single ended power transformer, said base terminalbeing connected to said first output of said control means, and saidemitter terminal being connected to the first capacitor of the inputfilter at its end opposite to said first inductor.
 6. The voltageconverter set forth in claim 5 wherein said second switching meanscomprises a second transistor having a second collector, a second baseand a second emitter terminal, said second collector terminal beingconnected to said other end of said primary winding of said secondsingle ended power transformer, said second base terminal beingconnected to said second output of said control means, and said secondemitter terminal being connected to the capacitor of the input filter atits end opposite to said first inductor.
 7. The voltage converter setforth in claim 6 wherein said power balancing means further comprises:athird resistor connected at its first end to the anode end of saidsecond diode element; a fourth resistor connected at its first end tothe anode end of said fourth diode element; a second capacitor connectedat its first end to the second end of said fourth resistor and connectedat its second end to a ground terminal; a first operational amplifierhaving a positive and negative input terminal and an output terminal,said positive input terminal connected to said second end of said fourthresistor, and said negative input terminal being connected to saidsecond end of said third resistor; a third capacitor having its firstend connected to said negative input terminal and having its second endconnected to said output terminal of said first operational amplifier.8. The voltage converter set forth in claim 7 wherein said control meansfurther includes:a first impedance network having a first and secondend, said first end being connected to said first terminal of saidoutput filter; a second operational amplifier having a positive andnegative input terminal and an output terminal, said positive inputterminal being connected to a reference voltage level, and said negativeinput terminal being connected to said second end of said firstimpedence network; a second impedance network having a first and secondend, said first end being connected to said negative input terminal ofsaid second operational amplifier and said second end being connected tosaid output of said second operational amplifier; a fifth resistorhaving its first end connected to the output terminal of said firstoperational amplifier; a sixth resistor having its first end connectedto the output terminal of said second operational amplifier and havingits second end connected to the opposite end of said fifth resistor; atwo phase oscillator having a first and a second output terminal, saidsecond output terminal producing an electrical waveform with the sameamplitude but 180° out of phase with respect to an electrical waveformpresent at the same time at said first output terminal; a first voltagecomparator having a positive and a negative input terminal and an outputterminal, said positive input terminal being connected to said secondend of said sixth resistor, and said negative input terminal beingconnected to said second output terminal of said two phase oscillator; afirst voltage driver having an input terminal and a first and secondoutput terminal, said input terminal being connected to said outputterminal of said first voltage comparator; a third single ended powertransformer having each end of its primary winding connected to each ofsaid first and second output terminals of said first voltage driver,respectively, and having one end of its secondary winding connected tothe base terminal of said second transistor, and having the other end ofits secondary winding connected to the emitter terminal of said secondtransistor; a second voltage comparator having a positive and a negativeinput terminal and an output terminal, said positive input terminalbeing connected to said output of said second operational amplifier, andsaid negative input terminal being connected to said first outputterminal of said two phase oscillator; a second voltage driver having aninput terminal and a first and second output terminal, said inputterminal being connected to said output terminal of said second voltagecomparator; a fourth single ended power transformer having each end ofits primary winding connected to each of said first and second outputterminals of said second voltage driver, respectively, and having oneend of its secondary winding connected to the base terminal of saidfirst transistor; and having the other end of its secondary windingconnected to the emitter terminal of said first transistor.
 9. Thevoltage converter set forth in claim 8 wherein said overload meansfurther includes:a seventh resistor having a first and second end, saidfirst end being connected to a negative reference voltage; an eighthresistor having a first and second end, said first end being connectedto said second end of said seventh resistor and said second end beingconnected to a ground terminal; a ninth resistor having a first and asecond end, said first end being connected to the anode end of saidsecond diode element; a tenth resistor having a first and a second end,said first end being connected to the anode end of said fourth diodeelement and said second end being connected to said second end of saidninth resistor; a fourth capacitor having a first and a second end, saidfirst end being connected to said second end of said tenth resistor, andsaid second end being connected to a ground terminal; a third voltagecomparator having a positive and a negative input terminal and an outputterminal, said positive input terminal being connected to said secondend of said seventh resistor, and said negative input terminal beingconnected to said second end of said ninth resistor. a fifth diodeelement having its anode end connected to the output terminal of saidthird voltage comparator; an eleventh resistor having a first and asecond end, said first end being connected to the cathode end of saidfifth diode element, and said second end being connected to a groundedterminal; a fifth capacitor having a first and a second end, said firstend being connected to said first end of said eleventh resistor, saidsecond end being connected to a ground terminal; a fourth voltagecomparator having a positive and a negative input terminal and an outputterminal, said positive input terminal being connected to said first endof said fifth capacitor, and said negative input terminal beingconnected to a positive reference voltage; a sixth diode element havingits anode end connected to the output terminal of said fourth voltagecomparator; a twelfth resistor having a first and a second end, saidfirst end being connected to the cathode end of said sixth diodeelement, and said second end being connected to the negative inputterminal of said second operational amplifier; a sixth capacitor havinga first and a second end, said first end being connected to the cathodeend of said sixth diode element, and said second end being connected toa ground terminal.